A ΔΣ D/A converter is known as an example of a D/A converter for converting a digital signal to an analog signal. FIG. 1A is a block diagram of a signal processing circuit 2r including a ΔΣ D/A converter. The ΔΣ D/A converter 100r includes a AE modulator 12, a dynamic element matching circuit 14 and a D/A converter 22. The ΔΣ modulator 12 ΔΣ-modulates an input digital data DIN. The D/A converter 22 converts a digital data output from the ΔΣ modulator 12, which has a gradation level from n+1 (0 to n) levels, to an analog voltage VOUT having a corresponding gradation level from corresponding n+1 (0 to n) levels.
FIG. 1B is a circuit diagram of the D/A converter 22 of a switched capacitor type, which is used in FIG. 1A. The D/A converter 22 includes n capacitors C1 to Cn, a plurality of switches CK1, CK2, SW1 to SWn and SWb1 to SWbn, an operational amplifier 26 and capacitors Cint and Cf. The n capacitors C1 to Cn have the same capacitance.
The D/A converter 22 alternates between a first state φ1 and a second state φ2 in synchronization with a clock. The switch CK1 is turned on in the first state φ1 and turned off in the second state φ2. The switch CK2 is turned on in the second state φ2 and turned off in the first state φ1.
Assuming that an input value to the D/A converter 22 is x, among the n switches SW1 to SWn, x switches are turned on and the remaining (n-x) switches are turned off. An ith (1 ≦i≦n) complementary switch SWbi operates in a complementary fashion to the corresponding switch SWi. At this time, in the first state φ1, x capacitors C1 are charged at a high level voltage VH-VM and the remaining (n-x) capacitors are charged at a low level voltage VL-VM. Subsequently, in the second state φ2, the n capacitors C1 to Cn are connected to the capacitors Cint and Cf. At this time, according to the conservation law of charge, an output voltage VOUT of the operational amplifier 26 is a voltage proportional to the number x of selected switches SW.
Returning to FIG. 1A, the dynamic element matching circuit 14 selects the x switches SW, which are to be turned on, in accordance to data output from the ΔΣ modulator 12. In an actual D/A converter 22, capacitances and switch impedances are not uniform. In order to eliminate this non-uniformity, the dynamic element matching circuit 14 dynamically switches cells (combinations of capacitors and switches) used cyclically or randomly. The dynamic element matching contributes to prevention of heat from concentrating at a certain portion in the D/A converter 22 and also to noise reduction.
Instead of the switched capacitor type, a current segment type, which is illustrated in FIG. 1C, may be used as the D/A converter 22. In this case, the D/A converter 22 includes a plurality of switches SW1 to SWn, a plurality of current sources CS1 to CSn, resistors Ri and Rf, a capacitor Cf and an operational amplifier 26. Assuming that an input value to the D/A converter 22 is x, among the n switches SW1 to SWn, x switches are turned on and the remaining (n-x) switches are turned off. Assuming that a unit current generated by one current CS is Ic, a voltage drop of the resistor Ri is Ri×Ic×x, which is in proportion to the input value x. The operational amplifier 26 inverts and amplifies the voltage of the resistor Ri. An output voltage VOUT of the operational amplifier 26 is a voltage proportional to the number x of selected switches SW.
An analog signal processing circuit 24 such as an amplifier or the like is provided in the subsequent stage of the D/A converter 22. In the signal processing circuit 2r, the ΔΣ modulator 12 and the dynamic element matching circuit 14 form a digital part 10, and the D/A converter 22 and the analog signal processing circuit 24 form an analog part 20.
The present inventor has studied the signal processing circuit 2r of FIG. 1A and has come to recognize the following problems. FIG. 2 is a graphical view showing noise characteristics of the ΔΣ D/A converter 100r of FIG. 1A. A solid line indicates a spectrum of the digital part 10. As for the spectrum of the digital part 10, a noise component is pushed away outside a signal band due to oversampling and noise shaping according to the ΔΣ modulation.
FIG. 2 shows a noise floor level of the digital part 10 and a noise floor level of the analog part 20. A dashed line indicates a spectrum of the entire signal processing circuit 2r including the digital part 10 and the analog part 20. An S/N ratio (i) of the entire signal processing circuit 2r is worse than the theoretical S/N ratio (ii) of only the digital part 10 by the noise floor of the analog part 20.